This patent pertains to methods of forming graded junction regions operatively adjacent transistor gates, methods of forming graded junction regions operatively adjacent transistor gates of CMOS circuitry, and methods of forming graded junction regions operatively adjacent peripheral NMOS transistor gates and operatively adjacent the transistor gates of a memory array. The patent also pertains to semiconductor transistor devices generally.
This invention grew out of a need to improve the methods of implanting graded junction regions within semiconductor devices and to thereby enhance production of integrated circuitry. Some typical types of graded junction regions are described with reference to FIG. 1.
In FIG. 1 is shown a semiconductor wafer fragment 10 comprising a portion of a semiconductor wafer material 12. Wafer 12 comprises an upper surface 13. Preferably, the semiconductor material of wafer 12 comprises conductively doped polysilicon. Above and within semiconductor wafer 12 is formed a transistor device 14. Device 14 comprises a gate 16, source/drain regions 18, and graded junction regions 20 and 22.
Gate 16 further comprises a gate oxide layer 24, a polysilicon layer 26, a refractory metal layer 28, an upper oxide layer 29, and a cap layer 30. Refractory metal layer 28 typically comprises a metal-silicide, such as tungsten silicide or titanium silicide, and cap layer 30 preferably comprises silicon nitride.
Gate 16 also comprises opposing lateral sidewalls 32. Sidewall spacers 34 are adjacent sidewalls 32 and comprise a sidewall spacer material, preferably silicon nitride. Sidewall spacers 34 comprise a lateral thickness xe2x80x9cXxe2x80x9d, which as measured at about the height of metal layer 28 is typically from about 200 Angstroms to about 1000 Angstroms.
Also, adjacent lateral sidewalls 32 is a silicon oxide layer 36. Silicon oxide layer 36 is generally formed by oxidizing the polysilicon of gate 16 and the polysilicon of upper surface 13 of wafer 12.
Source/drain regions 18 contain a conductivity enhancing dopant of a type dictated by the type of transistor device 14. If transistor device 14 is a P-channel Metal-Oxide Semiconductor (PMOS) field effect transistor, then source/drain regions 18 will comprise a p-type dopant. If, on the other hand, transistor device 14 is an N-channel Metal-Oxide Semiconductor (NMOS) field effect transistor, source/drain regions 18 will comprise n-type dopant.
Graded junction regions 20 and 22 are typically lightly doped drain (LDD) regions and halo regions. Generally, and preferably, the graded junction region extending nearest to gate 16, i.e., region 22, will be a halo region and the other graded junction region, i.e., region 20, will be an LDD region. However, the order of the graded junction regions can be reversed. Also, one or both of the graded junction regions may be eliminated in various transistor devices.
The LDD regions comprise conductivity enhancing dopant of the same conductivity type as the adjacent source/drain regions. Thus, in an NMOS device the LDD regions comprise n-type dopant and in a PMOS device the LDD regions comprise p-type dopant. The LDD regions reduce the electric field under gate 16 and thereby reduce the energy of hot electrons within transistor device 14. Such reduction in energy can reduce the damage caused to device 14 by hot electrons.
The halo regions comprise conductivity enhancing dopant of a different conductivity type than the adjacent source/drain regions. Thus, in an NMOS device the halo regions comprise a p-type dopant and in a PMOS device the halo regions comprise n-type dopant. The halo regions are used to improve the punch-through resistance of transistor device 14.
Referring to FIG. 2, a semiconductor wafer fragment 40 is illustrated at a processing step in accordance with the prior art. Fragment 40 comprises a portion of semiconductor wafer material 42. The semiconductor material of wafer 42 preferably comprises conductively doped polysilicon. The shown wafer fragment 40 is subdivided into three defined regions: PMOS region 44 (only a portion of which is shown), peripheral NMOS region 46, and memory array region 48 (only a portion of which is shown). Regions 44 and 46 together comprise a defined peripheral region 50 (only a portion of which is shown).
The semiconductor material of wafer 42 within peripheral NMOS region 46 and memory array region 48 is typically polysilicon lightly doped with a p-type impurity. The semiconductor material of wafer 42 within PMOS region 44 is typically polysilicon comprising a well 52 which is lightly doped with an n-type impurity.
A series of transistor gates 54, 56, 58 and 60 are provided on a top surface 61 of wafer 42. Gate 54 corresponds to a PMOS transistor gate, gate 56 corresponds to a peripheral NMOS transistor gate, and gates 58 and 60 correspond to memory array NMOS transistor gates. Also shown are field oxide regions 62 between the transistor gates and a word line 64 (only a portion of which is shown) over one of the field oxide regions. Gates 54, 56, 58 and 60, as well as word line 64, all comprise a gate oxide layer 66, a polysilicon layer 68, a refractory metal layer 70, an upper oxide layer 71, and a cap 72, as was described previously regarding transistor device 14. Further, each of gates 54, 56, 58, and 60, as well as word line 64, comprise opposing lateral sidewalls 63.
A prior art processing method of forming graded junction regions for the circuitry of FIG. 2 is described with reference to FIGS. 3-6.
Referring to FIG. 3, n-type regions 74 and 76 are implanted into peripheral and memory NMOS regions 46 and 48 respectively. Regions 74 are peripheral NMOS LDD regions implanted operatively adjacent peripheral NMOS gate 56, while regions 76 are memory array source/drain regions implanted operatively adjacent memory array NMOS gates 58 and 60. As the memory array source/drain regions 76 are typically implanted at a dopant concentration and depth comparable to the peripheral NMOS LDD regions 74, regions 74 and 76 are typically implanted during a common implant step.
Also referring to FIG. 3, p-type LDD regions are implanted operatively adjacent PMOS gate 54 to form PMOS LDD regions 78.
After the implant of regions 74, 76, and 78, the polysilicon of gates 54, 56, 58 and 60 as well as of word line 64 and upper surface 61 is oxidized to form the silicon oxide layer 80.
Referring to FIG. 4, a first masking layer provision step occurs as PMOS region 44 and memory array region 48 are covered with a masking layer 82, preferably of photoresist. Subsequently, a p-type dopant 84 is implanted into peripheral NMOS region 46 to form peripheral NMOS halo regions 86 operatively adjacent peripheral NMOS gate 56. Halo regions 86 are displaced further from gate 56 than LDD regions 74 as a result of LDD regions 74 being implanted prior to formation of oxide layer 80 and halo regions 86 being implanted subsequent to formation of oxide layer 80.
Referring to FIG. 5, masking layer 82 is removed and subsequently sidewall spacers 88, 90, 92, 94 and 96 are provided adjacent gates 54, 56, 58, 60 and word line 64, respectively.
Referring to FIG. 6, a second masking layer provision step occurs as PMOS region 44 and memory array region 48 are again masked, this time with a masking layer 98, preferably of photoresist. Subsequently, n-type dopant 100 is implanted into peripheral NMOS region 46 to form peripheral NMOS source/drain regions 102 operatively adjacent peripheral NMOS gate 56. Source/drain regions 102 are displaced further from gate 56 than graded junction regions 74 and 86 as a result of source/drain regions 102 being implanted subsequent to provision of sidewall spacers 90 and graded junction regions 74 and 86 being implanted prior to provision of sidewall spacers 90.
The net result of the steps shown in FIGS. 2-6 is to create a peripheral NMOS having source/drain regions 102, halo regions 86, and LDD regions 74, and to further create an array of NMOS memory device transistors having source/drain regions 76. Thus, the net result of the processing of FIGS. 2-6 is to create a peripheral NMOS transistor device 101 and an array of NMOS memory transistor devices 103.
The memory transistors 103 and peripheral NMOS transistor 101 are next typically further processed by: (1) deposition of a nitride or oxide cap over transistors 101 and 103 to block borophosphosilicate glass (BPSG) out-diffusion; (2) BPSG deposition over transistors 101 and 103; (3) the formation of contact openings to the source/drain regions of transistors 101 and 103; and (4) the provision of conductive plugs within the contact openings to form ohmic contacts with the source/drain regions.
A problem with the processing of FIGS. 3-6 is that the shown two separate masking steps (the masking steps of FIGS. 4 and 6) are utilized between the formation of the peripheral NMOS LDD region 74 (shown in FIG. 3) and the implant of source/drain regions 102 (shown in FIG. 6) during the formation of the peripheral NMOS transistor 101. As each masking step carries with it a risk of mask misalignment, it would be desirable to eliminate at least one of the masking steps. Also, and perhaps more importantly, as the cost of forming an integrated circuit increases as the number of masking steps is increased, it would be desirable to eliminate at least one of the masking steps.
Although the above discussion of prior art was limited toward applications in which the PMOS transistor gate and NMOS transistor gates were patterned concurrently (a so-called xe2x80x9cnon-split-polyxe2x80x9d process), similar masking steps, and associated desirability of eliminating masking steps, occur in applications in which a PMOS transistor gate is patterned non-concurrently with the NMOS transistor gates (the so-called xe2x80x9csplit-polyxe2x80x9d processes). A prior art split-poly process is described with reference to FIGS. 7-12.
Referring to FIG. 7, a semiconductor wafer fragment 240 is illustrated at a processing step in accordance with the prior art. Fragment 240 comprises a portion of a semiconductor material wafer 42, which is preferably the same type of semiconductor material as discussed previously regarding FIGS. 2-6. The shown wafer fragment 240 is subdivided into three defined regions: PMOS region 244 (only a portion of which is shown), peripheral NMOS region 246, and memory array region 248 (only a portion of which is shown). Regions 244 and 246 together comprise a defined peripheral region 250 (only a portion of which is shown).
The semiconductor material of wafer 42 within peripheral NMOS region 246 and memory array region 248 is typically polysilicon lightly doped with a p-type impurity. The semiconductor material of wafer 42 within PMOS region 244 is typically polysilicon comprising a well 252 which is lightly doped with an n-type impurity.
A series of field oxide regions 262 are provided on top of wafer 42. Between field oxide regions 262, and over a top surface 261 of wafer 42, is provided a gate oxide layer 266. Over gate oxide layers 266 and over field oxide regions 262 is provided a gate layer 253. Gate layer 253 typically comprises a polysilicon layer 268, a refractory metal layer 270, an upper oxide layer 271 and a cap 272.
Referring to FIG. 8, gate layer 253 is patterned over peripheral NMOS and memory array regions 246 and 248, while leaving layer 253 unpatterned over PMOS region 244. Accordingly, a series of transistor gates, 256, 258 and 260, are formed over regions 246 and 248 while leaving an unpatterned gate layer strip 251 over region 244. Also patterned is a word line 264 (only a portion of which is shown) over one of the field oxide regions of memory array region 248.
Gate 256 corresponds to a peripheral NMOS transistor gate and gates 258 and 260 correspond to memory array NMOS transistor gates. The gates, as well as word line 264, all comprise a gate oxide layer 266, a polysilicon layer 268, a refractory metal layer 270, an upper oxide layer 271, and a cap 272; structures which were described previously regarding transistor device 14. Also, each of gates 256, 258 and 260, as well as word line 264, comprise opposing lateral sidewalls 263.
Referring to FIG. 9, n-type regions 274 and 276 are implanted into peripheral and memory NMOS regions 246 and 248, respectively. Regions 274 are peripheral NMOS LDD regions implanted operatively adjacent peripheral NMOS gate 256, while regions 276 are memory array source/drain regions implanted operatively adjacent memory array NMOS gates 258 and 260. As the memory array source/drain regions 276 are typically implanted at a dopant concentration and depth comparable to the peripheral NMOS LDD regions 274, regions 274 and 276 are typically implanted during a common implant step.
After the implant of regions 274 and 276, the polysilicon of gates 256, 258 and 260, word line 264, upper surface 261 and unpatterned gate layer strip 251 is oxidized to form silicon oxide layer 280.
Referring to FIG. 10, a first masking layer provision step occurs as memory array region 248 is covered with a masking layer 282, preferably of photoresist. Subsequently, a p-type dopant 284 is implanted into peripheral NMOS region 246 to form peripheral NMOS halo regions 286 operatively adjacent peripheral NMOS gate 256. The PMOS region 244 is typically not covered by masking layer 282, as the cap layer 272 of unpatterned gate layer strip 251 is typically thick enough to effectively inhibit penetration of dopant 284 into the material beneath the cap layer 272.
Halo regions 286 are displaced further from gate 256 than LDD regions 274 as a result of LDD regions 274 being implanted prior to formation of oxide layer 280 and halo regions 286 being implanted subsequent to formation of oxide layer 280.
Referring to FIG. 11, masking layer 282 is removed. Subsequently, sidewall spacers 288, 290, 292, 294 and 296 are provided adjacent unpatterned gate layer strip 251, gates 256, 258 and 260, and word line 264, respectively. The sidewall spacers over the memory array region 248 will ultimately function to electrically insulate word line 264 from the memory devices encompassing memory transistors 258 and 260. The sidewall spacers over peripheral NMOS region 246, i.e., sidewall spacers 290, will ultimately function to space peripheral NMOS source/drain regions outwardly from gate 256 relative the graded junction regions 274 and 286, as shown in FIG. 12.
Referring to FIG. 12, a second masking layer provision step occurs as memory array region 248 is again masked, this time with a masking layer 298, preferably of photoresist. Subsequently, n-type dopant 300 is implanted into peripheral NMOS region 246 to form peripheral NMOS source/drain regions 302 operatively adjacent peripheral NMOS gate 256. As alluded to above with reference to FIG. 11, source/drain regions 302 are displaced further from gate 256 than graded junction regions 274 and 286 as a result of the use of sidewall spacers 290. More specifically, source/drain regions 302 are displaced further outward from gate 256 than regions 274 and 286 because regions 302 were implanted subsequent to the provision of the sidewall spacers 290 whereas regions 274 and 286 were implanted prior to provision of the sidewall spacers 290.
The net result of the processing of FIGS. 7-12 is to create a peripheral NMOS transistor device 301, an array of insulated NMOS memory transistor devices 303 and an insulated word line 307. The peripheral NMOS device 301 further comprising source/drain regions 302, halo regions 286, and LDD regions 274; and the array of NMOS memory device transistors 303 further comprising source/drain regions 276.
The memory transistors 303 and peripheral NMOS transistor 301 are next typically further processed by: (1) deposition of a silicon nitride or silicon oxide cap over transistors 301 and 303 to block borophosphosilicate glass (BPSG) out-diffusion; (2) BPSG deposition over transistors 301 and 303; (3) the formation of contact openings to the source/drain regions of transistors 301 and 303; and (4) the provision of conductive plugs within the contact openings to form ohmic contacts with the source/drain regions. Also, a PMOS transistor would typically be provided over PMOS region 244 by patterning unpatterned masking layer strip 251 to form a transistor gate and then providing source/drain regions, and possibly graded junction regions, operatively adjacent the transistor gate. The formed PMOS transistor and one or more of the NMOS transistors could be utilized in formation of CMOS circuitry.
A problem with the prior art processing sequence of FIGS. 7-12 is that two separate masking layer provision steps are utilized between the formation of the peripheral NMOS LDD region 274 (shown in FIG. 9) and the implant of source/drain regions 302 (shown in FIG. 12) which completes formation of the peripheral NMOS transistor device 301. As each masking layer provision step carries with it a risk of mask misalignment, it would be desirable to eliminate at least one of these two steps. Also, and perhaps more importantly, as the cost of forming an integrated circuit increases as the number of masking layer provision steps is increased, it would be desirable to eliminate at least one of these two steps.